TIMSK

Timer/Counter Interrupt Mask Register – TIMSK

Bits			Read/Write	Initial Value
7	TOIE1: Timer/Counter1, Overflow Interrupt Enable	When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the TOV1 flag, located in TIFR, is set.	R/W	0
6	OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable	When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the OCF1A flag, located in TIFR, is set.	R/W	0
5	OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable	When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the OCF1B flag, located in TIFR, is set.	R/W	0
4	-	-	R	0
3	ICIE1: Timer/Counter1, Input Capture Interrupt Enable	When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the ICF1 flag, located in TIFR, is set.	R/W	0
2	OCIE0B		R/W	0
1	TOIE0		R/W	0
0	OCIE0A		R/W	0